UNIT II- Peripherals and Interfacing CARITATEVOLE 8255

The parallel input-output port nick 8255 is also called since programmable peripheral input-output port. The Intel's 8255 is made for use with Intel's 8-bit, 16-bit and higher capability microprocessors. It includes 24 input/output lines which can be individually developed in two groups of twelve lines every single, or 3 groups of 8 lines. Both the groups of I/O pins are named as Group A and Group B. All these two teams contains a subgroup of eight I/O lines referred to as as 8-bit port and another subgroup of four lines or a 4-bit port. Thus Group A contains a great 8-bit interface A and also a 4-bit slot. C top.

PIO 8255

• The port A lines happen to be identified by symbols PA0-PA7 while the dock C lines are referred to as PC4-PC7. Similarly, GroupB is made up of an 8-bit port W, containing lines PB0-PB7 and 4-bit slot C with lower bits PC0- PC3. The dock C higher and slot C decrease can be used together as a great 8-bitport C. • The port C are designated the same talk about. Thus one may have possibly three 8-bit I/O ports or two 8-bit and two 4-bit slots from 8255. All of these ports can function separately either because input or as outcome ports. This is achieved by encoding the components of an internal enroll of 8255 called because control word register ( CWR ).

PIO 8255

• The interior block plan and the pin configuration of 8255 will be shown in fig. • The 8-bit data coach buffer can be controlled by the read/write control common sense. The read/write control logic manages all of the internal and external transactions of the two data and control words and phrases. • RD, WR, A1, A0 and RESET are the inputs furnished by the processor to the READ/ WRITE control logic of 8255. The 8-bit, 3-state bidirectional stream is used to interface the 8255 internal data shuttle bus with the exterior system data bus.

CARITATEVOLE 8255

• This barrier receives or perhaps transmits info upon the execution of input or perhaps output guidance by the microprocessor. The control words or status info is also moved through the buffer. • The signal information of 8255 are quickly presented the following: • PA7-PA0: These are eight port A lines that acts as either latched outcome or buffered input lines depending upon the control phrase loaded in the control phrase register. • PC7-PC4: Uppr nibble of port C lines. They could act as possibly output latches or insight buffers lines.

PIO 8255

• This port could also be used for generation of handshake lines in method 1 or mode installment payments on your • PC3-PC0: These are the reduced port C lines, other details are the same as PC7-PC4 lines. • PB0-PB7: They are the 8 port B lines which tend to be used as latched output lines or buffered input lines in the same way since port A. • RD: This is the type line influenced by the microprocessor and should end up being low to point read operation to 8255. • WR: This is an input series driven by microprocessor. A minimal on this range indicates publish operation.

FERVOROSO 8255

• CS: This is certainly a nick select series. If this kind of line will go low, it enables the 8255 to respond to RD and WR signals, normally RD and WR transmission are neglected. • A1-A0: These are the address insight lines and they are driven by microprocessor. These types of lines A1-A0 with RD, WR and CS through the following businesses for 8255. These address lines are used for addressing any one of the four subscribes, i. e. three slots and a control term register because given in desk below. • In case of 8086 systems, if the 8255 shall be interfaced with lower purchase data coach, the A0 and A1 pins of 8255 happen to be connected with A2 and A2 respectively.

RD 0 zero 0 0 RD you 1 one particular 1 RD X you

WR you 1 you 1 WR 0 0 0 0 WR By 1

CS 0 zero 0 zero CS 0 0 0 0 CS 1 zero

A1 0 0 1 1 A2 0 zero 1 one particular A1 Back button X

A0 0 1 0 you A0 zero 1 0 1 A0 X Back button

Input (Read) cycle Interface A to Data coach Port W to Data bus Interface C to Data coach CWR to Data tour bus Output (Write) cycle Info bus to Port A Data bus to Port B Data shuttle bus to Dock C Data bus to CWR Function Data bus tristated Data bus tristated

Control Term Register

PIO 8255.

• D0-D7: These kinds of...